The present invention generally relates to the field of chemical mechanical polishing (CMP). In particular, the present invention is directed to a CMP process that improves polishing performance.
In the fabrication of integrated circuits and other electronic devices on a semiconductor wafer, multiple layers of conducting, semiconducting and dielectric materials are deposited onto and etched from the wafer. Thin layers of these materials may be deposited by a number of deposition techniques. Common deposition techniques in modern wafer processing include physical vapor deposition (PVD) (also known as sputtering), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) and electrochemical plating. Common etching techniques include wet and dry isotropic and anisotropic etching, among others.
As layers of materials are sequentially deposited and etched, the surface of the wafer becomes non-planar. Because subsequent semiconductor processing (e.g., photolithography) requires the wafer to have a flat surface, the wafer needs to be periodically planarized. Planarization is useful for removing undesired surface topography as well as surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches and contaminated layers or materials.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize semiconductor wafers and other workpieces. In conventional CMP using a dual-axis rotary polisher, a wafer carrier, or polishing head, is mounted on a carrier assembly. The polishing head holds the wafer and positions it in contact with a polishing layer of a polishing pad within the polisher. The polishing pad has a diameter greater than twice the diameter of the wafer being planarized. During polishing, the polishing pad and wafer are rotated about their respective concentric centers while the wafer is engaged with the polishing layer. The rotational axis of the wafer is offset relative to the rotational axis of the polishing pad by a distance greater than the radius of the wafer such that the rotation of the pad sweeps out an annular “wafer track” on the polishing layer of the pad. When the only movement of the wafer is rotational, the width of the wafer track is equal to the diameter of the wafer. However, in some dual-axis polishers, the wafer is oscillated in a plane perpendicular to its axis of rotation. In this case, the width of the wafer track is wider than the diameter of the wafer by an amount that accounts for the displacement due to the oscillation. The carrier assembly provides a controllable pressure between the wafer and polishing pad. During polishing, a slurry, or other polishing medium, is flowed onto the polishing pad and into the gap between the wafer and polishing layer. The wafer surface is polished and made planar by chemical and mechanical action of the polishing layer and polishing medium on the surface.
The interaction among polishing layers, polishing media and wafer surfaces during CMP is being increasingly studied in an effort to optimize polishing pad designs. Most of the polishing pad developments over the years have been empirical in nature. Much of the design of polishing surfaces, or layers, has focused on providing these layers with various patterns of voids and arrangements of grooves that are claimed to enhance slurry utilization or adjust polishing uniformity. Over the years, quite a few different groove and void patterns and arrangements have been implemented. Prior art groove patterns include radial, concentric circular, Cartesian grid and spiral, among others. Prior art groove configurations include configurations wherein the width and depth of all the grooves are uniform among all grooves and configurations wherein the width or depth of the grooves varies from one groove to another. These groove patterns and configurations, however, overlook the utilization of slurry related to CMP polishers having active wafer carrier rings.
Recently, G. P. Muldowney, in US Pat. Pub. No. 2008/0182493, disclosed a low-slurry groove that functions by aligning polishing pad grooves with channels in the carrier ring over a plurality of locations to increase slurry utilization. This patent teaches polishing pad and carrier ring combinations that reduce the squeegee effect at the leading edge of the wafer, wherein much of the film of liquid, e.g., slurry, on the pad texture is swept off by the carrier ring. The patent further states that “The loss of this potentially usable slurry may reduce the effectiveness and predictability of the polishing process, while resulting in significant additional process costs.”
While the low-slurry groove pattern of Muldowney increases slurry utilization and reduces the squeegee effect of carrier rings having channels, there remains a need for CMP polishing processes that provide effective removal rate with improved polishing performance when using carrier rings having no channels. Polishing pad designers are continually seeking groove patterns and polishing methods that increase removal rate for increasing tool throughput and facilitate improved polishing performance for increasing wafer yields.